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By Zayden R., August 26, 2026
SiFive engineer Kito Cheng has contributed patches to the GCC to add -mcpu=native and -mtune=native support for RISC-V. This aligns RISC-V with other architectures, allowing better CPU-specific optimizations.
In a notable advancement for RISC-V development, SiFive engineer Kito Cheng has submitted patches to the GNU Compiler Collection (GCC) that introduce support for the -mcpu=native and -mtune=native options. These additions are significant as they bring RISC-V in line with other architectures that already leverage these options for optimizing code specifically for the CPU of the local system.
The introduction of these native tuning options means that GCC can now automatically detect and optimize for the specific RISC-V CPU core in use. This is particularly useful for developers seeking to squeeze the most performance out of their systems, as the compiler can now tailor its output to the exact capabilities of the host CPU. While it's unfortunate that this support has taken so long to materialize, its arrival is a welcome development for the RISC-V community.
However, there are some limitations to be aware of. The current patches do not yet support hybrid or asymmetric CPU core designs within the RISC-V ecosystem. This means that while single-core optimizations are now more accessible, developers working with more complex CPU designs will need to wait for further updates.
The patches also enhance GCC's ability to identify specific RISC-V cores, including the SiFive P550, P870-D, U74, and Spacemit X60, X100, and A100 cores. This improvement in core identification is crucial for ensuring that optimizations are as effective as possible. The community hopes that these patches will be integrated into the upcoming GCC 17 release, scheduled for next year.
For developers working with RISC-V, these updates to GCC could be a solid improvement, providing a more streamlined and effective way to optimize applications for their specific hardware configurations. As RISC-V continues to gain traction, such enhancements are crucial in ensuring that it remains competitive with other established architectures.
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