News › linux
By The Linux Camp News, October 4, 2026
An October 2 patch series targets TLB invalidation, performance monitoring and interrupt handling. The reported failures include incomplete invalidation, interrupt storms and a possible CPU-core hang.
Fujitsu's Tomohiro Misono submitted a four-patch Linux arm64 series on October 2, 2026, adding MONAKA CPU identification and three proposed hardware-erratum workarounds. They cover translation-cache invalidation, performance monitoring and interrupt handling. In the sources retrieved October 4, the established development is a patch submission, not a released kernel fix. 2
The CPU-identification change supplies a shared MONAKA definition for the TLB and performance-monitoring patches. Misono says the three workarounds are otherwise functionally independent: they are packaged together because two use that definition and all update Linux's silicon-errata documentation. This is not one failure spreading across three subsystems, but three separate errata being addressed in one submission. 2
The memory-management issue concerns the TLB, the processor's cache of address translations. According to Phoronix, range-based TLBI instructions, which invalidate cached translations, can fail to remove entries when targeting a virtual address or intermediate physical address. The proposed workaround issues additional invalidation instructions to finish the job. Both the cover letter and Phoronix identify 64K-page kernels as the relevant configuration; the supplied evidence does not identify other page sizes as affected by this particular erratum. 1 2
Performance monitoring has a separate reliability concern. Phoronix reports that the performance monitoring unit, or PMU, can incorrectly detect an overflow and potentially cause an interrupt storm. The series identifies its perf workaround as E#030002. The reported consequence is therefore more than an inaccurate measurement, but the supplied cover letter does not establish which monitoring configurations trigger it or how the correction works. 1 2
The interrupt-handling failure has a different chain of events. Phoronix reports that a software-generated interrupt, or SGI, can be lost if its generation races with higher-priority interrupt processing, a pending-interrupt update or a processing element entering sleep. The associated system-register write then fails to complete, potentially hanging the issuing CPU core. The series lists a GICv3 interrupt-controller workaround as E#030003, but its implementation is not included in the supplied patch bodies. 1 2
For MONAKA operators, the practical inference is to check the running kernel's page-size configuration when assessing the TLB issue, while tracking the perf and interrupt workarounds separately. A non-64K configuration should not be treated as clearance for all three errata: the page-size restriction is attached only to the TLB workaround. The supplied sources do not establish equivalent configuration-based exclusions for the other two. 2 1
Misono based the series on v7.3-rc5. That identifies the development baseline, not a fixed release or an affected-version range. As of the October 4 retrieval, this packet does not establish a merge, distribution backport or available update. Before treating a deployment as covered, seek confirmation that the applicable workarounds are in the running kernel, rather than relying on its base version or an installed package alone. Affected silicon revisions and workaround performance costs also remain unestablished here. 2